1. Field of the Invention
The present invention relates to semiconductor devices and methods of forming the same and, more particularly, to phase changeable memory cells and methods of forming the same.
2. Description of Related Art
Nonvolatile memory devices retain their stored data even when their power supplies are turned off and thus nonvolatile memory devices have been widely used in conjunction with computers, mobile telecommunication systems, memory cards and so on. For example, one widely used type of nonvolatile memory device is the flash memory device. Many flash memory devices employ memory cells having a stacked gate structure. The stacked gate structure of a flash memory device typically includes a tunnel oxide layer, a floating gate, an inter-gate dielectric layer and a control gate electrode, which are all sequentially stacked on a channel region. Further, to enhance the reliability and program efficiency of flash memory cells, the film quality of the tunnel oxide layer should be improved and the coupling ratio of the flash memory cell should be increased.
Recently, other types of nonvolatile memory devices, for example, phase changeable memory devices are being used in place of flash memory devices. A unit cell of a phase changeable memory device typically includes a switching device and a data storage element serially connected to the switching device. The data storage element of a phase changeable memory device includes a lower electrode electrically connected to the switching device, a phase change material pattern disposed on the lower electrode, and an upper electrode disposed on the phase change material pattern. In general, the lower electrode functions as a heater. For instance, when a write current flows through the switching device and the lower electrode, heat, measured in joule energy units, is generated at an interface between the phase change material pattern and the lower electrode. The heat measured in joule energy units converts the phase change material pattern into an amorphous state or a crystalline state.
FIG. 1 is a cross-sectional view illustrating a portion of a conventional phase changeable memory cell.
Referring to FIG. 1, a lower interlayer dielectric layer 3 is provided on a semiconductor substrate 1. The semiconductor substrate 1 is electrically connected to a contact plug 5, which passes through the lower interlayer dielectric layer 3. The contact plug 5 acts as a lower electrode. A phase change material pattern 7 is stacked on the lower interlayer dielectric layer 3 to cover the lower electrode 5 In addition, a top surface of the phase change material pattern 7 is in contact with an upper electrode 9. The upper electrode 9 is self-aligned with the phase change material pattern 7 to have the same width as the phase change material pattern 7.
The phase change material pattern 7 may be formed of a chalcogenide material layer, such as a GeSbTe layer (hereinafter, referred to as a GST layer). The GST layer easily reacts with a conductive material layer, such as a polysilicon (poly-Si) layer. For example, when the GST layer is in direct contact with a poly-Si layer, silicon atoms in the poly-Si layer permeate into the GST layer thereby increasing the resistance of the GST layer. As a result, the characteristics of the GST layer are degraded. Accordingly, the lower and upper electrodes 5 and 9, which are in direct contact with the phase change material pattern 7, are formed of stable conductive layers that do not react with the phase change material pattern 7. For example, a metal nitride layer such as a titanium nitride layer is widely used in formation of the lower and upper electrodes 5 and 9.
Moreover, the entire surface of the semiconductor substrate 1 having the upper electrode 9 is covered with an upper interlayer dielectric layer 11. A plate line 13 is disposed on the upper interlayer dielectric layer 11 and electrically connected to the upper electrode 9 through a plate line contact hole 11a that passes through the upper interlayer dielectric layer 11.
To store desired data in a phase changeable memory cell having the phase change material pattern 7, a write current IW should flow through the upper electrode 9, the phase change material pattern 7 and the lower electrode 5. A portion 7a of the phase change material pattern 7, which is in contact with the lower electrode 5, may be changed to a crystalline or amorphous state according to the amount of the write current IW. Also, the plate line contact hole 11a may typically have a width smaller than that of the upper electrode 9. However, despite the above-mentioned variations which may be made to the conventional phase change memory cell, the write current IW will still uniformly flow through the entire region of the upper electrode 9 as shown in FIG. 1 because the upper electrode 9 has a lower resistivity than the phase change material pattern 7. Therefore, the write current density in the bulk region of the phase change material pattern 7 of the above conventional phase change memory cell is lower than at the interface between the lower electrode 5 and the phase change material pattern 7 thereby degrading the phase transition efficiency in the bulk region of the phase change material pattern 7 of these conventional devices.
Another conventional phase changeable memory cell is disclosed in U.S. Pat. No. 6,545,903 to Wu, entitled “Self-Aligned Resistive Plugs for Forming Memory Cell with Phase Change Material”. The phase changeable memory cell described in the Wu patent includes a first highly resistive material layer and a second highly resistive material layer which are provided underneath and on top of a phase change material layer respectively In addition, a first low resistive plug and a second low resistive plug, which are self-aligned with each other, are disposed in the first and second highly resistive material layers, respectively. The first and second highly resistive material layers are formed of poly-Si or amorphous silicon (a-Si), and the self-aligned low resistive plugs are formed by implanting impurity ions into the highly resistive material layers using an ion implantation process. Consequently, the phase change material layer of the phase changeable memory cell described in the Wu patent is in direct contact with silicon layers, which in turn causes the characteristics of the interfaces between the phase change material layer and the silicon layers of this conventional memory cell to be unstable.